1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to data processing systems in which write transactions to a bus slave are interleaved such that write data of a plurality of co-pending write transactions is received in a variable order by the bus slave.
2. Description of the Prior Art
It is known to provide data processing systems including one or more bus masters connected by a communication bus (possibly a multi-channel bus) to one or more bus slaves. A write transaction is initiated by a bus master to a bus slave and includes separately transferring a write address from the bus master to the bus slave and the write data from the bus master to the bus slave.
In order to improve data throughput and processing capacity, high performance bus protocols can allow burst based addressing, (i.e., a single address is permitted per burst; address and data are de-coupled; a master is permitted to transmit a number of write addresses before transmitting the data. When using such a protocol, a slave can accept a number of co-pending write addresses, but must accept all the write data in the same order as the addresses were issued in order that the write data can be correlated with the write addresses.